Due to the development of the network transmission technology as well as the demands in the installed base of computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to recover data (clock signals) correctly.
At present, while data (clock) recovery is to be performed, a phase-locked loop is often utilized. During the data recovery process, usually the received data could be correctly recovered (read) by using a phase detector to synchronize the received data and recover the clock. In other words, the phase detector plays a very important role whether the data could be correctly recovered by a phase-locked loop.
FIG. 1 illustrates a prior art phase-locked loop for data recovery comprising a phase detector 11, a charge pump 12, a loop filter 13, and a voltage controlled oscillator 14. The phase detector 11 is used to receive a data (clock) signal from outside as well as a feedback clock signal CKvco from the voltage controlled oscillator 14. The phase detector 11 compares the two signals, in accordance with their phase difference θe (θe=θdata−θclock), a control signal up or dn will be output to control the charge pump 12. As shown in FIG. 2(a), when the transition edge of the data (clock) signal data leads the falling edge of the feedback clock signal CKvco, the phase detector outputs an up signal. On the other hand, as shown in FIG. 2(b), when the transition edge of the data (clock) signal data lags behind the falling edge of the feedback clock signal CKvco, the phase detector 11 outputs a dn signal. The charge pump 12 is controlled by the up and dn control signals output from the phase detector 11 to perform charge/discharge operations, and generates a voltage signal Vd. The loop filter 13 receives the voltage signal Vd and generates an appropriate voltage Vc for controlling the voltage controlled oscillator 14. The voltage controlled oscillator 14 receives the voltage Vc and generates a clock signal CKvco to be input to the phase detector 11.
As shown in FIG. 3, the phase detector 11 of the phase locked loop 1 is constituted by four flip-flops 111, 112, 113,114, and two OR gates 115, 116. The flip-flops 111 and 112 receive the complement of data from outside (denoted by data) and the data itself (denoted by data), respectively. The clock signal CKvco from the voltage controlled oscillator 14 is applied to the inversion reset terminals (rb) of the flip-flops 111 and 112 such that two control signals up1 and up2 are generated, respectively. The flip-flops 113 and 114 receive the complement of data from outside (denoted by data) and the data itself (denoted by data), respectively. The complement of the clock signal CKvco (denoted by CKvco) from the voltage controlled oscillator 14 is applied to the inversion reset terminals (rb) of the flip-flops 113 and 114 such that two control signals dn1 and dn2 are generated, respectively. According to the two signals up1 and up2, the OR gate 115 generates a control signal up for controlling the charge pump 12 (refer to FIG. 2(a)). Similarly, the OR gate 116 generates a control signal dn for controlling the charge pump 12 according to the two signals dn1 and dn2 (refer to FIG. 2(b))
Referring to FIG. 1, the voltage Vd is substantially controlled by the signals (up, dn). In other words, the variation of the control voltage Vd is related to the phase error θe. FIG. 4 illustrates the relation between the variation of Vd and the phase error θe. As shown in FIG. 4, when the data signal data has a phase lagging behind the clock signal CKvco, the smaller the phase error θe is, the more the voltage Vd varies. Therefore, phase error θe is theoretically supposed to approximate to zero and closely moves around the origin when the phase-locked loop is going to enter a phase-locked state. However, due to the above phenomenon, when the data signal data of the phase-locked loop has a phase lagging behind the clock signal CKvco, an obvious variation of Vd will be generated, which leads to clock jitter. And, the tolerance for data random jitter becomes worse. In other words, it is difficult to reduce the clock jitter for conventional phase-locked loops, large data random jitter is thus unaccepted.